1. Field of the Invention
Embodiments of this invention relate generally to computers, and, more particularly, to a method and apparatus for a power gateable retention storage element.
2. Description of Related Art
Computer circuitry has evolved from relatively simple, basic implementations to complex, high-speed designs. An increase in speed, features and capabilities of modern communications, computing and processing devices has driven computer circuitry to consume more power in many areas. Such power-intensive circuit designs have been a challenge for designers and a problem for consumers, for example, in mobile devices where battery life may be negatively affected by such power-intensive circuit designs. Similarly, products like desktop and laptop computers, computer monitors and the like have increased in size, complexity and speed. Devices with sleep, low-power and/or standby modes (hereinafter, low-power mode) have attempted to ameliorate battery life and power consumption issues by allowing such devices to consume less power when not in use by users.
Typically, at a computer circuit level, modern communications, computing and processing devices are based upon standard building blocks such as latches, flip-flops, combinatorial logic, buffers and inverters, transistors and the like. Storage elements like latches and flip-flops hold values when they are powered on, but lack the ability to maintain stored values when powered off. Current circuit implementations attempt to reduce this problem by off-loading stored values into “shadow latches” or “shadow registers” while a device is in a low-power mode. These implementations allow the latches and flip-flops to be powered down but have drawbacks. For example, off-loading stored values to shadow latches increases the size of the circuit footprint because a shadow latch must be included in addition to each regular storage element. Increased footprint size/complexity may have a negative effect on circuit routing as well. Additionally, shadow latches also consume power in order to maintain any stored values. Another drawback of using shadow latches is that when a device comes out of its low-power mode, the values stored in the shadow latches must be reloaded into the regular latches and flip-flops before the pre-power down state can be realized. This reloading requires time, and thus power, as well as the circuitry necessary to control the reloading.